<!doctype html><html lang=en><head><meta charset=utf-8><meta name=viewport content="width=device-width,initial-scale=1,viewport-fit=cover"><base href=https://www.lowrisc.org><link rel=icon type=image/png sizes=32x32 href=/favicon.png><title>Running simulations &middot; lowRISC: Collaborative open silicon engineering</title><link href=/main.21c9d.css rel=stylesheet><script type=application/javascript>var doNotTrack=false;if(!doNotTrack){(function(i,s,o,g,r,a,m){i['GoogleAnalyticsObject']=r;i[r]=i[r]||function(){(i[r].q=i[r].q||[]).push(arguments)},i[r].l=1*new Date();a=s.createElement(o),m=s.getElementsByTagName(o)[0];a.async=1;a.src=g;m.parentNode.insertBefore(a,m)})(window,document,'script','https://www.google-analytics.com/analytics.js','ga');ga('create','UA-53520714-1','auto');ga('send','pageview');}</script></head><body><header><nav class="navbar navbar-expand-md navbar-light"><div class=container><a class=navbar-brand href=#><img src=/img/logo/logo-dualcolor.svg alt=lowRISC></a>
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FPGA. Alternatively, they can be run without full OS support either in
a pure bare metal mode or with the support of the
<a href=https://sourceware.org/newlib/>newlib</a>
library (a C standard library implementation) and a simple proxy kernel.</p><h3 id=bare-metal-mode:327a3da24a5b3d16347a954f2bd690e9>Bare metal mode</h3><p>Programs running in this mode have no library support. The host target
interface (HTIF) must be accessed directly by the program if necessary, e.g.
to print messages on the host terminal.</p><p>All the test cases found in
<code>lowrisc-chip/riscv-tools/riscv-tests/isa</code> are run in bare metal mode.
The success/fail status of each test is placed in the <code>tohost</code> CSR
which can be checked by the host. For more information, see
<code>lowrisc-chip/riscv-tools/riscv-tests/env/p/riscv_test.h</code></p><h3 id=newlib-proxy-kernel-pk:327a3da24a5b3d16347a954f2bd690e9>Newlib/Proxy Kernel (PK)</h3><p>Tests and systems not requiring access to a full-blown OS can be
compiled for use with the proxy kernel (PK) and newlib. The proxy
kernel simply proxies syscalls to the host over the host target
interface (HTIF). This provides support for commonly used functions
such as <code>printf()</code>.</p><p>The <code>riscv64-unknown-elf-gcc</code> GCC compiler produces code for use with
the PK and newlib.</p><h3 id=risc-v-linux:327a3da24a5b3d16347a954f2bd690e9>RISC-V Linux</h3><p>Alternatively, programs can be run under a booted Linux system. The programs
running on Linux have the full system support, such as pthread, time,
etc. However, the running time is much longer than the previous two due to the
requirement to boot Linux in the simulation environment.</p><h3 id=running-programs-on-the-software-simulators-and-fpgas:327a3da24a5b3d16347a954f2bd690e9>Running programs on the software simulators and FPGAs</h3><p>Regardless of the whether programs require full Linux support or not,
simulations can take place at different levels (e.g. functional,
cycle-accurate) or by first synthesizing an FPGA implementation. Obviously,
fast simulators or FPGA support is required when booting full operating
systems.</p><ul><li><a href=/docs/tagged-memory-v0.1/spike/>Using the Spike Simulator</a></li><li><a href=https://www.lowrisc.org/docs/tagged-memory-v0.1/emulator/>Using the C++ emulator generated by Chisel</a></li><li><a href=https://www.lowrisc.org/docs/tagged-memory-v0.1/verilog-asic-sim/>Simulating the Verilog (ASIC target) generated by Chisel</a></li><li><a href=https://www.lowrisc.org/docs/tagged-memory-v0.1/verilog-fpga-sim/>Simulating the Verilog (FPGA target) generated by Chisel</a></li></ul></div></main><footer class=lr-footer><div class=container><div class=row><div class="col-lg-2 d-none d-lg-block"><img src=/img/logo/logo-dualcolor.svg width=150px></div><div class=col><p>The text content on this website is licensed under a <a href=https://creativecommons.org/licenses/by/4.0/>Creative Commons Attribution 4.0 International License</a>, except where otherwise noted. No license is granted for logos or other trademarks. Other content &copy; lowRISC Contributors.</p><a href=/privacy-policy>Privacy and cookies policy</a>
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